1 Rupee S T: Supporting Innovation in VLSI and Semiconductors with Intelligence

Vaibbav Taraate,FounderWith constant adaptations, disruptions, and adjustments, businesses have naturally had other priorities to navigate, but that does not mean that corporate training has been forgotten. The role of learning and development (L&D) continues to broaden, with many learning leaders helping facilitate and support change initiatives in their organizations. Businesses have had to train their people to adjust and adapt throughout the year by being reactive, agile, and robust. 1 Rupee S T, an initiative started by VaibbhavTaraate, offers modular and corporate training programs in FPGA and ASIC design. The training sessions are designed to deliver practically-oriented information to the engineers.

VaibbhavTaraate has over 19 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He holds BE degree in Electronics and has also completed MTech in Aerospace Control and Guidance. Initially, he worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs. He has authored six manuscripts during year 2016 to 2020 in ASIC and FPGA designs and his books are published by Springer. However, to fulfil his passion for educating engineers and help them get a better knowledge of technology, he established 1 Rupee S T.

Unique Training Programs for Engineers
1 Rupee S T, a semiconductor training program at Rs.1, was started to help and support intelligent engineers. The training includes three types of courses which are corporate program, full-time course, and online courses. The company provides corporate training in various VLSI domains. This training has an innovative course structure such as video sessions, assignments, test series, and exercises.
These training programs help the engineers to improve their technical strengths and get awareness about the latest trends in the VLSI domain. Afterward, in a full-time course, the training is provided only after clearing written tests and interviews.

After getting through the written test, there is a six-round interview that combines a basic understanding of system design, interfacing techniques, specification understanding, and basic architecture design, puzzle round, innovation round, and personal discussion and offer to join the course. If the students score 80 percent or above 80 percent in the selection test and interview, they have to pay only Rs. 1 plus 18 percent GST and the duration of the course is four months. But the major worry and the real observation during past three years is that most of the engineers are unable to clear the written test and not able to qualify for the SOC course with RS.1. Hence this initiative has started the affordable paid modular and summer training programs. These courses are benefited to most of the graduates to start from the foundation!

The training includes three types of courses which are corporate program, full-time course, and online courses

If they score 60 percent to 80 percent, then the investment will be Rs. 84,000 plus 18 percent GST. The course duration is eight months (4 months to cover the essential prerequisites required and four months for SOC design training and SOC implementation). Lastly, online courses in association with Iversity (part of Springer Nature) have launched few PRO and Expresso courses. Most of the methods cover the design concepts with tool-based optimization and practical scenarios. The online courses include digital design in VLSI perspective, RTL design using Verilog, STA and timing for VLSI beginners, and performance improvement techniques for design. And many other ASIC and FPGA design courses are in production.

Established in 2015, and not having the lavish kind of infrastructure still the 1 Rupee S T creates brain collateral in the VLSI and semiconductor design with the experts and professionals. Now days the lavish infrastructure is not especially important as the engineers can work from home as everybody has laptop and internet connectivity and that is what we do at 1 Rupee ST! Let the engineers and students should learn from home in that way they can well educated about the corporate culture also! For benefit of the engineers and humanity the company imparts training inVLSI, FPGA, ASIC, and entrepreneurship development with social inclination. We encourage students to use opensource tools and the free available FPGA tools with objective to innovate the products and new ideas.

We have invested on the FPGA bords and most of the engineers are using the FPGA boards with their laptops with freely available FPGA tools. This kind of education is beneficial to learn, apply and innovate the new products and ideas! “I wish to impart free of cost training in SOC design and product development. Also, through my company I want to establish the infrastructure to support the primary and secondary school education in rural areas and penetrate the thought of innovation, research, and development ! Even through my company I want to create the brain collateral in VLSI design and AI/ML.”, stated VaibbavTaraate, Founder, 1 Rupee S T.